`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:19:34 10/21/2010 
// Design Name: 
// Module Name:    addr_up_logic 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module addr_up_logic(
			input clk,
			input addr_up,
			output [9:0] address,
			output over
    );


reg overflow;
reg [9:0] addr;
assign over = overflow;
assign address = addr;


always@( posedge clk )
begin
	if(  addr_up == 1'b1)
	begin
		addr <= addr + 1;					//load next data
	
		if( addr == 10'b1 )					//check for overflow
			overflow <= 1;
		else
			overflow <= 0;
	end
end

endmodule
